Relevant quote regarding Snapdragon X
“As this was the first full quarter of shipments for Snapdragon X Series PCs, we saw sequential growth of around 180% compared to Q2 2024. However, as a proportion of the total Windows market, the products remain very niche, at less than 1.5% share. The top shipping vendor was Microsoft, which has transitioned most of their Surface line to the platform. Behind them was Dell who has embraced the new platform quite strongly in terms of SKU count, followed by HP, Lenovo, Acer and Asus (all four with similar volumes).”
One of the reasons why it’s harder for x86 is because the instruction set is simply more complex. You either need a decoder to turn it into simpler instructions, or more hardware to handle the complex instructions, both of which increase the number of transitors, and therefore power draw until we create a room temp superconductor
Both RISC and CISC decode into micro-ops regardless. Read the article, it goes into detail, the diagrams make it pretty clear if you don’t want to read the whole article. Modern processors have no notable differences between RISC or CISC designs anymore in the way you described. The only thing RISC and CISC differs in is essentially just the interface that assemblers assemble code into. Which is different across ISAs anyways.
Thanks for taking the time to correct me. I shouldn’t rely on elementary knowledge from a BSc that discussed chips from 3 decades ago.